The present disclosure relates to a semiconductor memory device, and a technique of setting the potential of a bit line to a negative potential in a write operation.
With respect to a semiconductor memory device, known techniques set the potential of a bit line to a negative potential in a write operation to improve a write margin. For example, U.S. Pat. No. 7,486,540 discloses a configuration including a capacitive element 605 comprised of a MOS transistor. In a write operation with write data DB and a write control signal WE, the capacitive element 605 performs a step-down operation in accordance with control by a signal BSTB to set the potential of a bit line to a negative potential (see FIGS. 6 and 7). On the other hand, U.S. Pat. No. 9,378,788 discloses a configuration including a capacitive element 216 comprised of a MOS transistor. In a write operation with write data DATA_IN and a write control signal WRITE_EN, the capacitive element 216 performs a step-down operation to set the potential of a bit line to a negative potential (FIG. 3).